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Published By: IBM     Published Date: May 04, 2009
Intel faces a familiar challenge: do more with less. With compute capacity growing exponentially and chip size expectation shrinking, the new 5500 series delivers on both fronts. This white paper delivers test results that show increased performance and speed along with greater efficiency.
Tags : 
ibm, express seller, virtualization intel, xeon, processor, 5500, bladecenter, system x, power, energy costs, hardware, cooling, (eda) applications, quad-core processors, 64-bit intel® xeon® processor, pre-silicon verification, automation, global design team and collaboration, simulation synthesis, layout versus schematic
    
IBM
Published By: Mentor Graphics     Published Date: Sep 01, 2010
This paper will examine current methods used to eliminate waived errors at the chip level and describe a new automatable method for identifying and removing waived errors from DRC results.
Tags : 
mentor graphics, automated drc, violation waiver management, ip block integration, design rule checking, tcp/ip protocol, business process automation, data center design and management
    
Mentor Graphics
Published By: Mentor Graphics     Published Date: Sep 01, 2010
This paper will examine the implementation and demonstrate the benefits of eqDRC through a variety of examples comparing traditional DRC with eqDRC approaches.
Tags : 
mentor graphics, equation-based drc, nanometer design, design rule checks, drceqdrc
    
Mentor Graphics
Published By: Mentor Graphics     Published Date: Oct 08, 2014
This paper reports on common layout requirements related to SERDES designs, and how HyperLynx DRC can help identify issues on PCB boards that violate these requirements.
Tags : 
mentor graphics, boards, serdes, pcb boards, drc, gigabit networking, internetworking hardware, best practices, power and cooling
    
Mentor Graphics
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